When designing a PCB, one problem is how to route all connecting lines, and one particular problem arises when connecting a Central Processing Unit (CPU) to a memory chip. The memory chip is generally symmetric and has a plurality of pins. Each pin of the memory chip has to be connected to the CPU. Due to timing requirements, the connecting lines group wise or pairwise have to have identical length, and this is often done by using a T-branch topology. FIG. 1 shows PCB layout examples for a symmetrical and an asymmetrical T-branch topology. One disadvantage with the T-branch topology is that additional stubs and stubs length increase command and address line run lengths as well as data and strobe bus lengths. This will inhibit the speed at which signals are effectively transferred. More specifically, as address lines and data buses lengthen, transmission line effects increase which limits effective signal speeds. Furthermore, when more and more memory chips are used, and with many pins on each memory chip, it is a challenge to fit all connecting lines in a limited area of the PCB.
In U.S. Pat. No. 5,260,892, a method for doubling the density of Random Access Memory (RAM) chips without significantly increasing the signal trace length is demonstrated. As shown in FIG. 2 of the present disclosure, a RAM chip 65 is mounted to a double sided circuit board 66 with a mirror image RAM chip 67 mounted on the other side. The RAM chip 65 is identical to the mirror image RAM chip 67 except that the leads of the RAM chip are mirror images of the leads of the mirror image RAM chip. That is to say, in this example, looking from the top of the chips, the front left pin 68 of the RAM chip 65 serves the same electrical function as the front right pin 69 of the mirror image RAM chip 67. The RAM chip 65 and its mirror image RAM chip 67 are mounted opposite each other on the circuit board 66 in such a manner that the front left pin 68 of the RAM chip 65 is connected electrically to the front right pin 69 of the mirror image RAM chip 67 through the circuit board 66 by a via 70 which is also connected electrically to a signal trace 71 which serves both pins. Similarly, the second pin from the front 72 on the left side of the RAM chip 65 corresponds to the second pin from the front 73 on the right side of the mirror image RAM chip 67, etc.
However the trace 71 is on one side of the PCB, so there will be a difference in length of the total trace for RAM chip 65 and RAM chip 67, namely the length of the via. For a PCB with thickness of, e.g., 1.6 mm, this is quite a large difference. Such a thickness may correspond to a timing difference of 8-9 picoseconds, which should be compared to an accuracy of about 3 picoseconds required in many specifications. Further, the two RAM chips are still two separate chips. Moreover, there are still no such mirrored memory chips on the current market so that they could be used directly in pairs with one memory chip on each side of the PCB.